B. Communication Infrastructure

At the heart of the neurosynaptic core is a crossbar memory

that forms the synapses between axons and the neurons.

The crossbar array is configurable so that arbitrary networks

can be set up in the system (e.g. Axons 1, 2, and 3 are

connected to the first neuron in the 2D neuron array in Fig.

1). Each row of the crossbar corresponds to an axon, each

column corresponds to the input of a neuron (the dendrite),

and the junctions are binary synapses implemented by a two

terminal memory cell (e.g., SRAM). Thus each of the N

neurons may get up to K synaptic inputs depending on the

activity in the axons and the configuration of the crossbar.

We chose K as 1024 and N as 256 resulting in 1024Ч256

crossbar synapses and an enormous configuration space.

Spikes events are sent to and from the core using addressevent

representation (AER) packets [7]. On the output side,

an AER transmitter [8] encodes spiking activity by sending

the locations of active neurons through a multiplexed channel,

leveraging the fact that the bandwidth of wires (easily

larger than 100s of MHz) is orders of magnitude larger than

the bandwidth of biological axons (in the 10’s of Hz range).

The spikes can be sent off chip, or routed to an axon of

another core via a look-up table. On the input side, an AER

receiver delivers incoming spikes to the appropriate axon at

a predetermined time configured in a scheduler block. As

spikes are serviced sequentially, their addresses are decoded

to the crossbar where all 256 synaptic connections of an

active axon are read out in parallel.

C. Discrete-time Operation

An example sequence of operation in the core is illustrated

in Fig. 1. The operation has two phases during each time

step.

The positive edge of a global synchronization clock

(Sync) initiates the first phase of operation. In this phase,

address-events along with their time stamps are sent to

the core and are received by the scheduler. The scheduler

evaluates the time stamps and asserts the appropriate axons

that go into a token-ring. The units in the token-ring that

receive active axons assert the rows of the crossbar in a

mutually exclusive manner. Once a wordline in the crossbar

is activated all the neurons that are connected to the axon

(corresponding to the 1’s in the row) receive an input spike

along with information about the type of the axon. The

neurons update their voltages as axon events come in. The

first phase needs to complete within the first half of the

global synchronization clock (that usually has a period of 1

millisecond)—giving us a precise margin in which neural

updates need to complete for potentially all 1024 axon

inputs.

In the second phase of operation, the negative edge of

the synchronization clock is detected by all the neurons. On

receiving this event, neurons whose voltages have exceeded

their respective thresholds produce spikes in their output

ports. The spiking addresses are encoded by the AER

transmitter and sent out of the core sequentially. This phase

needs to complete within the other half of the global clock—

i.e. the AER transmitter has to guarantee that it can service

256 potential spikes within the global timestep.

A 1 millisecond global clock period (typical temporal

precision in biological neural networks) means that the

performance requirements of the circuits in the two phases

of operation are easily met. Breaking neural updates into

two phases ensures that the hardware is always in sync with

an equivalent software simulation at the end of each time

step. Specifically, the order in which address-events arrive

to the core or exit from the core can be variable due to

resource arbitration, especially when events are sent through

a non-deterministic routing network. To preserve one-to-one

correspondence, the different orderings must not influence

the spiking dynamics. We achieve one-to-one equivalence by

first accounting for all the synaptic events and then checking

for spikes.